Important Dates


Submission Due: September 14, 2022
Notification: October 20, 2022
Camera-ready Version: October 30, 2022
Conference: December 9-12, 2022

Important Links


Submission Link
Visa to India
Registration link


Sponsors & Co-Organizers




























Keynote Speakers



Ingrid Verbauwhede, KU Leuven, Belgium


Title: Hardware: an essential partner to cryptography


Abstract: Cryptography is a beautiful branch of mathematics with a nice purpose of providing information security. To be useful in practical applications, the algorithms runs on hardware or software, with software ultimately running also on hardware processors. This presentation covers multiple links of this relation between hardware and cryptography. The goal is to provide insights to the cryptographer, so that more efficient and secure cryptographic algorithms and protocols are developed. Important topics linking both include:
Hardware provides the means to accelerate the computationally demanding operations, as is currently the case for the new generation of post-quantum algorithms.
A very nice aspect of cryptography is that it reduces what needs to be kept secret to the keys, while the algorithms can be publicly known. The hardware is responsible to keep the key(s) secret. Side-channel, fault-attacks and other physical attacks make this a challenging task.
Provable Secure mathematical countermeasures against physical attacks rely on models to abstract how the hardware behaves. Unfortunately, the models are often the weak link between theory and practice and it results in broken implementations.
Hardware also provides essential building blocks to security. Protocols rely on nonces and freshness from random numbers. Generating full entropy random numbers is a challenge.
We can conclude that hardware is an essential partner to cryptography to provide the promised information security.

Bio: Dr. Ir. Ingrid Verbauwhede is a Professor in the research group COSIC at the KU Leuven. She is a fellow of IEEE and of IACR. She was elected as member of the Royal Academy of Belgium in 2011. She is a recipient of an ERC Advanced Grant in 2016 and a second one in 2021. She received the IEEE 2017 Computer Society Technical Achievement Award. She delivered the 2022 IACR distinguished lecture. She will receive the 2023 IEEE D. Pederson award of the SSCS society.
She is a pioneer in the field of efficient and secure implementations of cryptographic algorithms on many different platforms: ASIC, FPGA, embedded, cloud. With her research she bridges the gaps between electronics, the mathematics of cryptography and the security of trusted computing. Her group owns and operates an advanced electronic security evaluation lab. Her list of publications is available from her Google scholar profile.


Jeyavijayan Rajendran, TAMU, USA


Title: Building Secure Systems Bottom Up: Hunting down hardware security vulnerabilities.


Abstract: Hardware is at the heart of computing systems. For decades, software was considered error-prone and vulnerable. However, recent years have seen a rise in attacks exploiting hardware vulnerabilities and exploits. Such vulnerabilities are prevalent in hardware for several reasons: First, the existing functional verification and validation approaches do not account for security, motivating the need for new and radical approaches such as hardware fuzzing. Second, existing defense solutions, mostly based on heuristics, do not undergo rigorous red-teaming exercises like cryptographic algorithms; I will talk about how emerging artificial intelligence (AI) can rapidly help red-team such techniques. Last and most important, students and practitioners who are typically trained in designing, testing, and verification are not rigorously trained in cybersecurity -- for many reasons, including a lack of resources, time, and methodologies; I will talk about how AI can be incorporated into (hardware) cybersecurity education.


Bio: Jeyavijayan (JV) Rajendran is an Assistant Professor in the Department of Electrical and Computer Engineering at the Texas A&M University. He obtained his Ph.D. degree from New York University in August 2015. His research interests include hardware security and computer security. His research has won the NSF CAREER Award in 2017, ONR Young Investigator Award in 2022, the IEEE CEDA Ernest Kuh Early Career Award in 2021, the ACM SIGDA Outstanding Young Faculty Award in 2019, the Intel Academic Leadership Award, the ACM SIGDA Outstanding Ph.D. Dissertation Award in 2017, and the Alexander Hessel Award for the Best Ph.D. Dissertation in the Electrical and Computer Engineering Department at NYU in 2016, along with several best student paper awards. He organizes and has co‐founded Hack@DAC, a student security competition co-located with DAC, and SUSHI.



Chester Rebeiro, IIT Madras, India


Title: Towards Secure Computing Systems


Abstract: Over the last four decades, microprocessor research has focused on improving performance. Various micro architectural features such as cache memories, branch prediction, superscalar, speculative and out-of-order execution, were developed to facilitate this. Side-by-side, features such as multiprogramming, multicore and hardware multithreading were incorporated to increase throughput. These features allowed multiple users to simultaneously share a processor. To isolate one user’s program from another, rudimentary security schemes such as protection rings and page table access controls bits were used. Very soon it was realized that these security schemes were insufficient. Vulnerabilities in software permitted user space programs to gain privileged access. Shared hardware became a source of information leaks that could undermine the isolation provided. The very features in the processor that were incorporated to boost performance and throughput have now become a security liability.
Hardening microprocessors for security requires rethinking of processor design, where security is considered as a primary design criteria along with performance, energy, and area. This is quite a challenge because incorporating security often comes with significant overheads. Tradeoffs would need to be made to achieve sufficient security with acceptable overheads in the other design parameters. Furthermore, security threats can arise across the computing stack — from hardware, micro-architecture, to system and application software. One solution will not fix all threats; each threat would need to be handled separately. In this talk, we will discuss some of our recent and ongoing research in developing secure microprocessors. We will discuss Hardware enabled memory protection schemes and the design of power attack protected microprocessors; micro-compartments, and support for functional programming languages that can considerably reduce software vulnerabilities.


Bio: Chester Rebeiro is an Associate Professor at the Indian Institute of Technology, Madras. Prior to this he was a postdoctoral researcher at Columbia University. He has a Ph.D. from IIT Kharagpur in the area of hardware security. Before joining IIT Kharagpur, he worked as a Member Technical Staff at CDAC, Bangalore. His area of interests includes security aspects in the operating system, architecture, and VLSI. He is particularly interested in applying learning algorithms and formal methods to analyze the security of systems.



Nele Mentens, KU Leuven, Belgium


Title: Security challenges and opportunities in emerging device technologies


Abstract: While traditional chips in bulk silicon technology are widely used for reliable and highly efficient systems, there are applications that call for devices in other technologies. On the one hand, novel device technologies need to be re-evaluated with respect to potential threats and attacks, and how these can be faced with existing and novel security solutions and methods. On the other hand, emerging device technologies bring opportunities for building the secure systems of the future. This talk gives an overview of the minimal hardware resources that are needed to build secure systems and of the state of the art in security research in emerging device technologies.


Bio: Nele Mentens is a professor at Leiden University and KU Leuven. Her research interests are in the field of configurable computing and hardware security. She was/is the PI in around 25 finished and ongoing research projects with national and international funding. She serves/served as a program committee member of many renowned international conferences on security and hardware design (e.g. NDSS, USENIX Security Symposium, ACM CCS, Asiacrypt, Eurocrypt, CHES, ESORICS, DAC, DATE, FPL, ESSCIRC). She was the general co-chair of FPL'17 and the program chair of EWME'18, PROOFS'18, FPL'20, CARDIS'20, RAW'21 and VLSID'22. She will be the program chair of FPL, ASAP and DDECS in 2023. She is (co-)author in over 150 publications in international journals, conferences and books. She received best paper awards and nominations at CHES'19, AsianHOST'17 and DATE'16. Nele serves as an associate editor for IEEE CAS Magazine, IEEE S&P, IEEE TCAD, ACM TODAES and ACM TRETS. She works as an expert for the European Commission.



Sanjay K. Jha, UNSW, Sydney


Title: Security Challenges in Internet of Things (IoT) and Cyber-Physical Systems (CPS)


Abstract: In this talk, I will introduce the broad range of research under the UNSW Institute for Cyber Security. Then I will discuss technical work close to the title of this talk: on how the community is converging towards the IoT vision having worked in wireless sensor networking and Machine-2-Machine (M2M) communication. This will follow a general discussion of security challenges in IoT. I will discuss some results from my recent projects on security in the IoT domain. This will include physical layer secure key generation, and application of advanced ML techniques to event spoofing attacks, and traffic obfuscation to investigate the privacy of a Smart Home. I will conclude my talk with a description of a new project on Distributed Energy Resource Management Security.


Bio: Sanjay K. Jha is the Chief Scientist of the UNSW Institute for Cybersecurity (IFCYBER) and a full Professor at the School of Computer Science and Engineering, UNSW Sydney. Sanjay has published over 300 articles in high-quality journals and conferences. He leads UNSW's participation in the cooperative research centre for cybersecurity CSCRC. He is interested in research at the intersection of networking, both wired and wireless and application security using Machine learning. He was an editor of the IEEE Transactions on Dependable and Secure Computing (TDSC). He has been a member of the technical program committee of the ACM WiSec 2014 and ACM CCS'2014/19, AsiaCCS’23 Codaspy20/21 security conferences. More about his research is availabe here




Tutorial Speakers




Łukasz Chmielewski, Radboud University The Netherlands


Title: Attacking Real-World Crypto with Side-Channel Analysis


Abstract: : Modern cryptography has produced a multitude of ciphers that protect our daily lives including secure authentication, electronic transactions, etc. However, once the cipher is implemented on a physical device (microprocessor, FPGA, ASIC, etc.) it becomes vulnerable to side-channel and fault attacks. Side-channel attacks pose a unique challenge as an intersection of cryptography, electronics, and statistics and pervading all aspects of modern hardware security. The attackers monitor closely the power consumption or electromagnetic emission of a cryptographic device and they are able to extract the secret key using statistical techniques. This tutorial will provide an overview of various classes of side-channel attacks, showcasing the core techniques for key recovery. During the tutorial, the students will get the chance to develop some basic side-channel analysis tools in Python. Subsequently, they will use the tools to attack real-world datasets aiming at secret key extraction.


Bio: Łukasz Chmielewski is an assistant professor in the Centre for Research on Cryptography and Security (CRoCS) at Masaryk University and a part-time postdoctoral researcher in the Digital Security Group at Radboud University Nijmegen. He mainly works in the field of physical attacks, both side-channel analysis (SCA) and fault injection (FI). In particular, his main research interests lie in SCA of public-key cryptosystems. He also has significant commercial experience in SCA, FI, and software-security evaluations of embedded devices. His overall practical experience in physical attacks spans over 10 years.



Lejla Batina , Radboud University The Netherlands


Title: Profiling Side-channel Analysis: From Template Attack to Deep Learning


Abstract: Modern cryptography has produced a multitude of secure ciphers that protect our daily electronic transactions. However, once the cipher is implemented on a physical device (microprocessor, FPGA, ASIC, etc.) it becomes vulnerable to side-channel attacks. Side-channel attacks pose a unique challenge as an intersection of cryptography, electronics, and statistics and pervading all aspects of modern hardware security. The attacks monitor closely the power consumption or electromagnetic emission of a cryptographic device and they are able to extract the secret key using statistical techniques. More recently, we are witnessing the uprise of deep learning techniques in SCA, even for targets protected with countermeasures. In this tutorial, we will start with template attacks and progress to the machine learning and deep learning techniques, finishing with state-of-the-art and future challenges


Bio: TBD



Stjepan Picek, Radboud University The Netherlands


Title: Profiling Side-channel Analysis: From Template Attack to Deep Learning


Abstract: Modern cryptography has produced a multitude of secure ciphers that protect our daily electronic transactions. However, once the cipher is implemented on a physical device (microprocessor, FPGA, ASIC, etc.) it becomes vulnerable to side-channel attacks. Side-channel attacks pose a unique challenge as an intersection of cryptography, electronics, and statistics and pervading all aspects of modern hardware security. The attacks monitor closely the power consumption or electromagnetic emission of a cryptographic device and they are able to extract the secret key using statistical techniques. More recently, we are witnessing the uprise of deep learning techniques in SCA, even for targets protected with countermeasures. In this tutorial, we will start with template attacks and progress to the machine learning and deep learning techniques, finishing with state-of-the-art and future challenges


Bio: Stjepan Picek is an associate professor at Radboud University, The Netherlands. His research interests are security/cryptography, machine learning, and evolutionary computation. Prior to the associate professor position, Stjepan was an assistant professor at TU Delft, and a postdoctoral researcher at MIT, USA and KU Leuven, Belgium. Stjepan finished his PhD in 2015 with a topic on cryptology and evolutionary computation techniques. Stjepan also has several years of experience working in industry and government. Up to now, Stjepan has given more than 30 invited talks and published more than 150 refereed papers. He is a program committee member and reviewer for a number of conferences and journals, and a member of several professional societies. His work has been featured in the mainstream media and on popular technology blogs.



Sikhar Patranabis, IBM Research, India


Title: Zero-Knowledge Proofs in Practice: Demystifying Blockchain Rollups


Abstract: How does one convince you that a Sudoku puzzle is solvable without revealing the solution itself? Can someone convince you that they own a bitcoin without revealing the actual bitcoin? Sounds impossible? Zero-knowledge proof (ZKP) is a revolutionary cryptographic technique that enables the seemingly impossible, such as the above.
In a more real-world setting, ZKP allows a cloud server to convince its clients about the correctness of an expensive computation, while making minimal demands on the clients’ storage and compute capabilities. It turns out that this capability is what makes ZKP the “secret sauce” behind one of the trendiest buzzwords in the blockchain world - the “rollups”.
In this tutorial, we will walk the participants through an interactive and (hopefully) fun hands-on exercise of building a demo rollup on a toy Ethereum network (with “fake” Ether as the cryptocurrency). The entire tutorial will use a gamut of open-source tools for emulating a blockchain network (e.g., Ganache), interacting with the blockchain network (e.g., Truffle), and generating, verifying, deploying ZKPs in smart contracts (using Circom and SnarkJS). We will combine these tools to achieve the end-goal of implementing a prototype rollup system that illustrates the core challenges behind popular layer-2 offerings from Polygon, zkSync etc. We will conclude by foreshadowing an alternative approach to designing rollups that extends the ideas in the tutorial, and is plausibly more scalable in certain settings.

In addition to the above interactive exercise, we will also provide the necessary background on blockchain rollups and ZKPs. The content of the tutorial should be accessible to CS/ECE/EE undergraduates. No background in cryptography will be assumed. Some basic familiarity with blockchain is likely to be useful, though not mandatory.

The presenters also acknowledge Abhishek Singh (research engineer at IBM Research India) for his contributions and support towards the material presented in the tutorial.


Bio: Sikhar Patranabis is an advisory research scientist at IBM Research India. His research interests span all aspects of theoretical and applied cryptography, with special focus on quantum-safe cryptographic techniques for privacy-preserving computation, blockchain interoperability and decentralized trust. Prior to joining IBM, he was a staff research scientist at Visa Research USA. He received his B.Tech and PhD from IIT Kharagpur, India, and has held a postdoctoral position at ETH Zurich, Switzerland. His recognitions include an IACR best paper award at Asiacrypt 2022, an IBM PhD fellowship, a Qualcomm Research Innovation Fellowship, and the President of India gold medal from IIT Kharagpur in 2015.



Nitin Singh, IBM Research, India


Title: Zero-Knowledge Proofs in Practice: Demystifying Blockchain Rollups


Abstract: How does one convince you that a Sudoku puzzle is solvable without revealing the solution itself? Can someone convince you that they own a bitcoin without revealing the actual bitcoin? Sounds impossible? Zero-knowledge proof (ZKP) is a revolutionary cryptographic technique that enables the seemingly impossible, such as the above.
In a more real-world setting, ZKP allows a cloud server to convince its clients about the correctness of an expensive computation, while making minimal demands on the clients’ storage and compute capabilities. It turns out that this capability is what makes ZKP the “secret sauce” behind one of the trendiest buzzwords in the blockchain world - the “rollups”.
In this tutorial, we will walk the participants through an interactive and (hopefully) fun hands-on exercise of building a demo rollup on a toy Ethereum network (with “fake” Ether as the cryptocurrency). The entire tutorial will use a gamut of open-source tools for emulating a blockchain network (e.g., Ganache), interacting with the blockchain network (e.g., Truffle), and generating, verifying, deploying ZKPs in smart contracts (using Circom and SnarkJS). We will combine these tools to achieve the end-goal of implementing a prototype rollup system that illustrates the core challenges behind popular layer-2 offerings from Polygon, zkSync etc. We will conclude by foreshadowing an alternative approach to designing rollups that extends the ideas in the tutorial, and is plausibly more scalable in certain settings.

In addition to the above interactive exercise, we will also provide the necessary background on blockchain rollups and ZKPs. The content of the tutorial should be accessible to CS/ECE/EE undergraduates. No background in cryptography will be assumed. Some basic familiarity with blockchain is likely to be useful, though not mandatory.

The presenters also acknowledge Abhishek Singh (research engineer at IBM Research India) for his contributions and support towards the material presented in the tutorial.


Bio: Nitin Singh is a senior research scientist at IBM Research India, working in the area of applied cryptography with focus on privacy preserving machine learning, decentralized identity etc, employing cryptographic techniques such as zero knowledge proofs and multiparty computation. Nitin completed his Bachelors and Masters in Computer Science from IIT Delhi and later obtained a PhD in Mathematical Sciences from Indian Institute of Science, Bangalore in 2014. In between, he has worked as a Software Engineer at VMware and Veritas.



Matthias Kannwischer , Academica Sinica Taiwan


Title: Implementing Kyber and Dilithium


Abstract: In July 2022, the US National Institute of Standards and Technology (NIST) announced the first set of post-quantum schemes to be standardized: Kyber, Dilithium, Falcon, and SPHINCS+. It is expected that NIST will publish its first post-quantum cryptography standard including those schemes soon. This tutorial will cover the implementation of the lattice-based key-encapsulation mechanism Kyber and the digital signature scheme Dilithium. I will introduce the core construction of the schemes and essential implementation techniques. This will cover number-theoretic transforms, Montgomery multiplication, and Plantard multiplication.
Participants will then implement their own number-theoretic transforms for Kyber and Dilithium using Arm Cortex-M4 assembly. Instructions will be provided to functionally test the implementations on an Arm Cortex-M4 emulated using qemu (version 5.2 or newer). For measuring the performance, a small number of STM32F407 development boards will available during the tutorial.
Participants should follow the pre-tutorial instructions available at the Github link. In particular, please install arm-none-eabi-gcc, qemu, and st-link. The 'helloworld' program should successfully run on qemu before the tutorial.


Bio: Matthias Kannwischer is a post-doctoral researcher at Academia Sinica in Taipei, Taiwan. He received his MSc in IT Security from TU Darmstadt in 2017 and defended his doctoral thesis on Polynomial Multiplication for Post-Quantum Cryptography at Radboud University in April 2022. His research focuses on the implementation of post-quantum cryptography, in particular lattice-based cryptography on Arm processors. He is one of the creators of pqm4 - a benchmarking and testing framework for post-quantum cryptography on the Cortex-M4.